The present invention relates to a device for monitoring balanced two-wire bus lines and two-wire bus interfaces for serial data transmission, the bus lines and the bus interfaces having first and second line conductors that change their polarity in antiphase in the normal state.
Balanced two-wire bus lines and balanced interfaces or bus drivers are widely used to transmit digital information on serial paths. In this case, the binary data are transmitted via, for example, line conductors twisted with one another; the conductors are driven in antiphase in this case. Various measures are known for testing the defect-free availability of such lines and of the line drivers driving them as well as of the line receivers connected thereto. For example, test bits are inserted into messages to be transmitted, and the operability of the bus line and of the transmitting interface is checked by devices connected to the bus by verifying the proper reception of the test bits. Another approach is to send test telegrams via the bus line at a predetermined time interval. Devices connected to the bus then check whether the test messages are received within the system-specific fixed time interval, with the result that, when they are lacking, it can be concluded that there is a defect in the bus system. Another approach is to use monitoring electronics to monitor the potential difference between the conductors of such a bus line or the potentials on the line conductors and to test the extent to which corresponding voltage values lie outside the state change times inside a defined tolerance window.
A disadvantage in all these known solutions is the relatively high outlay on hardware and software.
It is therefore an object of the invention to provide a device for monitoring balanced two-wire bus lines and two-wire bus interfaces which manages with a low outlay, functions independently of potential differences such as, for example, a ground offset between individual bus stations, and can be realized using standard technology and is integratable on a semiconductor chip.
This and other objects are achieved by the present invention which provides a device for monitoring balanced two-wire bus lines and two-wire bus interfaces for serial data transmission, the bus lines and the bus interfaces having first and second line conductors that change their polarity in antiphase in the normal state. The device comprises first, second and third comparison means, the first comparison means having a positive input operationally connected to the first bus conductor and a negative input connected to a reference potential. The second comparison means has a negative input connected to the second bus conductor and a positive input connected to the reference potential. The third comparison means has an input side connected to the first and second bus conductors. A first shift register or counter having a clock input is operationally connected to an output of the first comparison means. A second shift register or counter having a clock input is operationally connected to an output of the second comparison means. Means for conditioning signal edges to form pulses are provided. The means for conditioning are connected downstream of the third comparison means and have an output connected to reset inputs of the shift registers or counters. The shift registers or counters each have at least one output. A first error status signal relating to the first bus conductor is at a first one of the outputs, and a second error status signal relating to the second bus conductor is at a second one of the outputs.
The device according to the invention comprises first, second and third comparison means for comparing the wire potentials with one another and with a fixed reference voltage, and two shift registers or counters as well as at least one pulse generator for deriving reset pulses from the changes of sign from the intercomparison of the potentials of the two bus conductors. The shift registers or counters are reset at the same time by the reset pulses. In order to shift or increment the shift registers or counters respectively, they can be fed the result signals produced by the comparison of the bus potentials with a fixed reference voltage. The register length or number of counter stages in this case determines the depth of bit error tolerance of the device. The logic state of the respectively last-reached state of appropriately selected outputs of the shift registers or counters characterizes in this case the most recent, still detectable error state of the bus conductor which clocks the respective other shift register or counter.
Thus, in accordance with certain preferred embodiments, the pulse generator can be implemented from a few logic gates. Static error signals, that is to say error signals which, after occurring, are not volatile in conjunction with the disappearance of bus errors, are delivered by a device developed in accordance with other embodiments certain embodiments perform automatic resetting after a temporary disturbance of even only one conductor. Certain developments of the invention benefit the integrability of the device and certain developments allow the forming of a programmable device, which to that extent is particularly universal and suitable for large-scale integration. The device can be designed as a standard cell. The device can be operated as a test receiver for analyzing bus disturbance in cooperation with software routines of a decentral bus test system.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.